module par_ser_beh2 (sh_clk, rst, load, par_in, ser_out);
   input       sh_clk;  // shift clock
   input       rst;     // reset signal
   input       load;    // load enable
   input [7:0] par_in;  // parallel input
   output      ser_out; // serial output

   reg       ser_out;

   reg       busy;      // busy flag
   reg       done;      // done flag
   reg [3:0] count;     // shift counter
   reg [7:0] p_reg;     // input register


always @(posedge rst) begin
   busy = 1'b0;
   done = 1'b0;
   count = 4'h0;
   p_reg = 8'h00;
end
    
always @(posedge load or posedge done)
begin
   if (done && busy)
      busy <= 1'b0;

   if (load && !busy)
   begin
      p_reg <= par_in;
      busy <= 1'b1;
   end
end

always @(posedge busy or posedge sh_clk)
begin
   if (busy)
      if (!count[3])
      begin
         done <= 1'b0;
         count <= count + 1'b1;
         ser_out <= p_reg[count];
      end
      else
      begin
         done <= 1'b1;
         count <= 4'h0;
      end
end
                          
endmodule